There has been popularized an A/D converter of a time interleaving manner which has a plurality of A/D converting units performing A/D conversion equivalently and at high speed, each A/D converting unit operating at timings shifted from one another.
If a plurality of A/D converting units have exactly the same electrical characteristics, the A/D converter will have the same A/D conversion characteristics as those of an A/D converter having a single A/D converting unit. However, actually, variation in the A/D conversion characteristics occurs even when the A/D converting units are formed on the same semiconductor chip.
The variation in A/D conversion characteristic is caused by three factors of direct-current offset, gain error, and sampling time error. In these factors, direct-current offset and gain error can be detected and corrected by a relatively simple method known as a conventional method. However, there is no established method to detect and correct a sampling time error.
A prior art concerning the sampling time error shows an example where sampling time errors of a plurality of A/D converting units are estimated so that each A/D converting unit corrects the sampling time. Also, it has been proposed to arrange a complicated filter to estimate the sampling time error of each A/D converting unit. However, when the structure of the filter becomes complicated, the circuit scale of the A/D converter is increased, which leads to the increase in power consumption.
In another proposed technique, a reference A/D converting unit is arranged to output a reference signal, and the output signals of the other A/D converting units are compared to the reference signal, in order to simplify the calculation for estimating the error of each A/D converting unit. In this technique, the output signal of the reference A/D converting unit influences the accuracy of the entire system. Further, the reference A/D converting unit to be arranged separately increases the circuit scale of the A/D converter.